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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">CTIDEVID, CTI Device ID register 0</h1><p>The CTIDEVID characteristics are:</p><h2>Purpose</h2>
        <p>Describes the CTI component to the debugger.</p>
      <h2>Configuration</h2><p>CTIDEVID is in the Debug power domain.
    </p><h2>Attributes</h2>
        <p>CTIDEVID is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="6"><a href="#fieldset_0-31_26">RES0</a></td><td class="lr" colspan="2"><a href="#fieldset_0-25_24">INOUT</a></td><td class="lr" colspan="2"><a href="#fieldset_0-23_22">RES0</a></td><td class="lr" colspan="6"><a href="#fieldset_0-21_16">NUMCHAN</a></td><td class="lr" colspan="2"><a href="#fieldset_0-15_14">RES0</a></td><td class="lr" colspan="6"><a href="#fieldset_0-13_8">NUMTRIG</a></td><td class="lr" colspan="3"><a href="#fieldset_0-7_5">RES0</a></td><td class="lr" colspan="5"><a href="#fieldset_0-4_0">EXTMUXNUM</a></td></tr></tbody></table><h4 id="fieldset_0-31_26">Bits [31:26]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-25_24">INOUT, bits [25:24]</h4><div class="field">
      <p>Input/output options. Indicates presence of the input gate. If the CTM is not implemented or CTIv2 is not implemented, this field is RAZ.</p>
    <table class="valuetable"><tr><th>INOUT</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p><a href="ext-ctigate.html">CTIGATE</a> does not mask propagation of input events from external channels.</p>
        </td></tr><tr><td class="bitfield">0b01</td><td>
          <p><a href="ext-ctigate.html">CTIGATE</a> masks propagation of input events from external channels.</p>
        </td></tr></table>
      <p>All other values are reserved.</p>
    </div><h4 id="fieldset_0-23_22">Bits [23:22]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-21_16">NUMCHAN, bits [21:16]</h4><div class="field"><p>Number of ECT channels implemented. For Armv8, valid values are:</p>
<ul>
<li><span class="binarynumber">0b000011</span> 3 channels (0..2) implemented.
</li><li><span class="binarynumber">0b000100</span> 4 channels (0..3) implemented.
</li><li><span class="binarynumber">0b000101</span> 5 channels (0..4) implemented.
</li><li><span class="binarynumber">0b000110</span> 6 channels (0..5) implemented.
</li></ul><p>and so on up to <span class="binarynumber">0b100000</span>, 32 channels (0..31) implemented.</p>
<p>All other values are reserved.</p>
<p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p><p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-15_14">Bits [15:14]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-13_8">NUMTRIG, bits [13:8]</h4><div class="field">
      <p>Upper bound for number of triggers. The indices of all implemented input and output triggers are less than this value.</p>
    <p>All other values are reserved. If the PE contains a Trace extension, this field must be at least <span class="binarynumber">0b001000</span>. There is no guarantee that all of the input and output triggers, including the highest numbered, are connected to any components, or that the implementation of input and output triggers is symmetrical.</p>
<p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p><p>Access to this field is <span class="access_level">RO</span>.</p></div><h4 id="fieldset_0-7_5">Bits [7:5]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-4_0">EXTMUXNUM, bits [4:0]</h4><div class="field">
      <p>Number of multiplexors available on triggers. This value is used in conjunction with External Control register, <a href="ext-asicctl.html">ASICCTL</a>.</p>
    
      <p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p>
    <p>Access to this field is <span class="access_level">RO</span>.</p></div><h2>Accessing CTIDEVID</h2><h4>CTIDEVID can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>CTI</td><td><span class="hexnumber">0xFC8</span></td><td>CTIDEVID</td></tr></table><p>Accesses on this interface are <span class="access_level">RO</span>.</p><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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